HAL OSPI types migration

This section provides information about the HAL OSPI types migration.

Note

The TypeDef suffix used in HAL1 is replaced by the _t in HAL2.

Related concept: Replaced TypeDef suffix with _t in type names

HAL OSPI callback ID type definition

HAL1

HAL2 

typedef enum
{
  HAL_OSPI_ERROR_CB_ID
  HAL_OSPI_ABORT_CB_ID
  HAL_OSPI_FIFO_THRESHOLD_CB_ID
  HAL_OSPI_CMD_CPLT_CB_ID
  HAL_OSPI_RX_CPLT_CB_ID
  HAL_OSPI_TX_CPLT_CB_ID
  HAL_OSPI_RX_HALF_CPLT_CB_ID
  HAL_OSPI_TX_HALF_CPLT_CB_ID
  HAL_OSPI_STATUS_MATCH_CB_ID
  HAL_OSPI_TIMEOUT_CB_ID
  HAL_OSPI_MSP_INIT_CB_ID
  HAL_OSPI_MSP_DEINIT_CB_ID
} HAL_OSPI_CallbackIDTypeDef;

  • Removed from HAL2 : the callback registration is managed by dedicated functions for each OSPI event. For more details, see : HAL OSPI register callback

  • HAL_OSPI_MSP_INIT_CB_ID and HAL_OSPI_MSP_DEINIT_CB_ID are removed because the functions HAL_OSPI_MspInit() and HAL_OSPI_MspDeInit() are removed.

Related concepts:

HAL OSPI initialization type definition

HAL1

HAL2 

/* */







typedef struct
{
  uint32_t MemoryMode;
  uint32_t MemoryType;
  uint32_t MemorySize;
  uint32_t WrapSize;
  uint32_t ClockMode;
  uint32_t ChipSelectBoundary;





  uint32_t ClockPrescaler;
  uint32_t SampleShifting;
  uint32_t DelayHoldQuarterCycle;
  uint32_t ChipSelectHighTimeCycle;
  uint32_t MaxTran;
  uint32_t Refresh;
  uint32_t DelayBlockBypass;


  uint32_t FifoThresholdByte;


  uint32_t FreeRunningClock;
} OSPI_InitTypeDef;

typedef struct
{
 hal_xspi_memory_config_t memory;
 hal_xspi_timing_config_t timing;
 hal_xspi_hyperbus_config_t hyperbus
} hal_xspi_config_t;

/* Memory structure */
typedef struct
{
  hal_xspi_memory_mode_t mode;
  hal_xspi_memory_type_t type;
  hal_xspi_memory_size_t size_bit;
  hal_xspi_wrap_size_t wrap_size_byte;
  hal_xspi_clock_polarity_t clock_polarity;
  hal_xspi_cs_boundary_t cs_boundary;
} hal_xspi_memory_config_t;

/* Timing structure */
typedef struct
{
  uint32_t clk_prescaler;
  hal_xspi_sample_shift_t shift;
  hal_xspi_delay_hold_t hold;
  uint32_t cs_high_time_cycle;
  uint32_t cs_release_time_cycle;
  uint32_t cs_refresh_time_cycle;
  hal_xspi_dlyb_state_t dlyb_state;
} hal_xspi_timing_config_t;

HAL_XSPI_SetFifoThreshold(hal_xspi_handle_t *hxspi, uint32_t threshold);
HAL_XSPI_GetFifoThreshold(const hal_xspi_handle_t *hxspi);

HAL_XSPI_EnableFreeRunningClock(hal_xspi_handle_t *hxspi);
HAL_XSPI_DisableFreeRunningClock(hal_xspi_handle_t *hxspi);

HAL OSPI auto polling mode configuration type definition

HAL1

HAL2 

typedef struct
{
  uint32_t Match;
  uint32_t Mask;
  uint32_t MatchMode;
  uint32_t AutomaticStop;
  uint32_t Interval;
} OSPI_AutoPollingTypeDef;

typedef struct
{
  uint32_t match_value;
  uint32_t match_mask;
  hal_xspi_match_mode_t match_mode;
  hal_xspi_automatic_stop_status_t automatic_stop_status
  uint32_t interval_cycle;
} hal_xspi_auto_polling_config_t;

HAL OSPI handle type definition

HAL1

HAL2 

OSPI_HandleTypeDef

hal_xspi_handle_t

Related concept: Renaming of the handle structure

HAL OSPI callback type definition

HAL1

HAL2 

pOSPI_CallbackTypeDef

hal_xspi_cb_t

HAL OSPI hyperbus configuration type definition

HAL1

HAL2 

typedef struct
{
  uint32_t RWRecoveryTimeCycle;
  uint32_t AccessTimeCycle;
  uint32_t WriteZeroLatency;
  uint32_t LatencyMode;
} OSPI_HyperbusCfgTypeDef;

typedef struct
{
  uint32_t rw_recovery_time_cycle;
  uint32_t access_time_cycle;
  hal_xspi_write_zero_latency_status_t write_zero_latency;
  hal_xspi_latency_mode_t latency_mode;
} hal_xspi_hyperbus_config_t;

HAL OSPI hyperbus command type definition

HAL1

HAL2 

typedef struct
{
  uint32_t AddressSpace;
  uint32_t Address;
  uint32_t AddressWidth;
  uint32_t DataLength;
  uint32_t DQSMode;
} OSPI_HyperbusCmdTypeDef;

typedef struct
{
  hal_xspi_addr_space_t         addr_space;
  uint32_t                      addr;
  hal_xspi_addr_width_t         addr_width
  uint32_t                      size_byte;
  hal_xspi_dqs_status_t         dqs_mode_status;
  hal_xspi_hyperbus_data_mode_t data_mode;
} hal_xspi_hyperbus_cmd_t;

HAL OSPI memory mapped mode configuration type definition

HAL1

HAL2 

typedef struct
{
  uint32_t TimeOutActivation;
  uint32_t TimeoutPeriodClock;
} OSPI_MemoryMappedTypeDef;

typedef struct
{
  hal_xspi_timeout_activation_t timeout_activation;
  uint32_t timeout_period_cycle;
} hal_xspi_memory_mapped_config_t;

HAL OSPI regular command type definition

HAL1

HAL2 

typedef struct
{
  uint32_t OperationType;
  uint32_t FlashId;
  uint32_t Instruction;
  uint32_t InstructionMode;
  uint32_t InstructionSize;
  uint32_t InstructionDtrMode;
  uint32_t Address;
  uint32_t AddressMode;
  uint32_t AddressSize;
  uint32_t AddressDtrMode;
  uint32_t AlternateBytes;
  uint32_t AlternateBytesMode;
  uint32_t AlternateBytesSize;
  uint32_t AlternateBytesDtrMode;
  uint32_t DataMode;
  uint32_t NbData;
  uint32_t DataDtrMode;
  uint32_t DummyCycles;
  uint32_t DQSMode;



  uint32_t SIOOMode;
  } OSPI_RegularCmdTypeDef;

typedef struct
{
  hal_xspi_operation_type_t operation_type;
  hal_xspi_io_select_t  io_select;
  uint32_t instruction;
  hal_xspi_instruction_mode_t instruction_mode;
  hal_xspi_instruction_width_t instruction_width;
  hal_xspi_instruction_dtr_status_t instruction_dtr_mode_status;
  uint32_t addr;
  hal_xspi_addr_mode_t addr_mode;
  hal_xspi_addr_width_t addr_width;
  hal_xspi_addr_dtr_status_t addr_dtr_mode_status;
  uint32_t alternate_bytes;
  hal_xspi_alternate_bytes_mode_t alternate_bytes_mode;
  hal_xspi_alternate_bytes_width_t alternate_bytes_width;
  hal_xspi_alternate_bytes_dtr_status_t alternate_bytes_dtr_mode_status;
  hal_xspi_regular_data_mode_t data_mode;
  uint32_t size_byte;
  hal_xspi_data_dtr_status_t data_dtr_mode_status;
  uint32_t dummy_cycle;
  hal_xspi_dqs_status_t dqs_mode_status;
} hal_xspi_regular_cmd_t;


HAL_XSPI_EnableSIOO(hal_xspi_handle_t *hxspi);
HAL_XSPI_DisableSIOO(hal_xspi_handle_t *hxspi);

HAL OSPI IO manager configuration type definition

HAL1

HAL2

In HAL1, there is only one structure, OSPIM_CfgTypeDef which is used to configure either port 1 or port 2.

In HAL2, the structure has been redesigned as hal_xspi_xspim_config_t, allowing configuration of both port 1 and port 2 simultaneously. 

typedef struct
{
  uint32_t ClkPort;
  uint32_t DQSPort;
  uint32_t NCSPort;
  uint32_t IOLowPort;
  uint32_t IOHighPort;
  uint32_t Req2AckTime;
} OSPIM_CfgTypeDef;

typedef struct
{
   struct
   {
    hal_xspi_xspim_port_t    clk;
    hal_xspi_xspim_port_t    dqs;
    hal_xspi_xspim_port_t    ncs;
    hal_xspi_xspim_io_t      io_low;
    hal_xspi_xspim_io_t      io_high;
   } port1;
   struct
   {
    hal_xspi_xspim_port_t    clk;
    hal_xspi_xspim_port_t    dqs;
    hal_xspi_xspim_port_t    ncs;
    hal_xspi_xspim_io_t      io_low;
    hal_xspi_xspim_io_t      io_high;
   } port2;
   uint32_t                  req_ack_cycle;
} hal_xspi_xspim_config_t;

HAL OSPI DLYB configuration type definition

Note

In HAL1, the dlyb was represented by ll_dlyb.h in the dlybcore. In HAL2, it has been moved to the core driver and renamed dlyb_core.h.

HAL1

HAL2 

#define HAL_OSPI_DLYB_CfgTypeDef      LL_DLYB_CfgTypeDef

typedef struct
 {
   uint32_t Units;
   uint32_t PhaseSel;
 } LL_DLYB_CfgTypeDef;

Removed from HAL2(Use instead delay block functions :
   - HAL_XSPI_DLYB_SetConfigDelay(hal_xspi_handle_t *hxspi, uint32_t clock_phase_value)
   - HAL_XSPI_DLYB_GetConfigDelay(const hal_xspi_handle_t *hxspi, uint32_t *p_clock_phase))